The present invention relates to a test circuit for a memory, and especially, to a test circuit for a memory of a semiconductor integrated circuit in which a memory and a logic section are mixedly loaded on one semiconductor chip.
In recent years, various kinds of LSIs in which a memory is mixedly loaded in a logic section such as an ASIC and a microprocessor have been proposed. In this kind of LSI, a normal operation of the memory is controlled by a signal from the logic section, and for example, when a read command is issued from the logic section, the memory outputs a data of a selected address to the logic section. Similarly, the memory outputs the data of the selected address to the logic section. In this kind of LSI, since to conduct a test of the memory through the complicated logic section is impractical, various exclusive test circuits for conducting a test of the memory have been proposed.
FIG. 10 is a view showing an arrangement of a conventional test circuit for a memory (Refer to a patent document 1 (JP-P2002-42493A (FIG. 5)).). In FIG. 10, 211 is a memory circuit that is an object of a test of the memory, and has a plurality of data input terminals DI and a plurality of data output terminals DO. 212 is an internal logic circuit having an external input terminal NI, and 213 and 214 are selectors, respectively, each of which switches input terminals A and B to each other by means of a switch control signal from a test mode terminal TEST.
Next, an operation will be explained. In case of writing a normal data, by means of a switch control signal from the test mode terminal TEST, both of the selectors 213 and 214 select the input terminals A. The normal data is input from the external input terminal NI, and is written into the memory circuit 211 from the data input terminal DI via the internal logic circuit 212 and the selector 213. Also, in case of reading the normal data, it is output from the data output terminal DO of the memory circuit 211 to an external output terminal OUT via the internal logic circuit 212 and the selector 214.
In case of writing a test data, by means of the switch control signal from the test mode terminal TEST, both of the selectors 213 and 214 select the input terminals B. The test data is input from a test input terminal TI, and is written into the memory circuit 211 from the data input terminal DI via the selector 213. Also, in case of reading the test data, it is output from the data output terminal DO of the memory circuit 211 to the external output terminal OUT via the selector 214.
In conducting a test of the memory, by means of the switch control of the selectors 213 and 214, such a conventional test circuit of the memory can conduct the test of the memory of a single piece of the memory circuit 211 without involving the internal logic circuit 212.
As a prior art of other test circuit of a memory, there is one known as a built-in self-test circuit (BIST circuit). While, in the above-mentioned test circuit of the memory, all of the generation of a test pattern and the analysis of an output data are conducted by an external tester, in the BIST circuit, a test pattern generator and a test result analyzer are provided, and only a determination result of the test is output to an external tester. Accordingly, in the BIST circuit, there is a merit that the number of terminals for the test, which are necessary for an LSI, requires a small number.
However, in the general BIST circuit, a sequencer is provided inside the memory test circuit, and since the sequencer controls test contents, the test contents are fixed, and it is impossible to change the test contents after a design of the LSI.
Accordingly, as a method of making it possible to change the test contents even after the design of the LSI, a programmable BIST circuit is considered. FIG. 11 is an arrangement view of a programmable BIST circuit that can be generally considered. To a memory 102 for a RAM test command, a program data 101 representing algorithm for generating the test contents is input from an external input terminal, and is stored therein. When a test mode setting signal TEST becomes predetermined logic, a RAM test control circuit 103 is set to a test mode, and operates in synchronization with a RAM test clock CLK, and provides an address specification signal 106 to the memory 102 for a RAM test command, and sequentially reads a program data 107 from the memory 102 for a RAM test command.
A test pattern generator 110 sequentially generates a test pattern data 111 corresponding to the program data in accordance with a control signal 108 output from the RAM test control circuit 103. The test pattern data 111 is switched to a signal 115 during a normal operation by means of a selector 114, and is selected as an input data to a memory 116 to be tested.
In such a programmable BIST circuit, by changing the program data being held in the memory for a RAM test command, it is possible to perform an arbitrary RAM test. Also, to avoid an area increase due to the RAM test command memory, a method has been proposed, in which a scan path register inside an LSI is substituted for the RAM test command memory (Refer to a patent document 2 (JP-P2001-297598A (FIG. 1)).).
In the method wherein, by means of conducting the switch control of the selector, the test of the memory circuit is conducted without involving the internal logic circuit, the terminals for a test, which corresponds to the numbers of the data input terminals and the data output terminals, are required. Accordingly, in case that a bit width of a data input or a data output is large or in case that a plurality of memories is integrated, there is a defect that a number of terminals for a test are required, which becomes impractical.
In the general BIST circuit, a sequencer is provided inside the circuit, and since the sequencer controls test contents, the test contents are fixed, and it is impossible to change the test contents after a design of the LSI. On the other hand, in the BIST circuit as shown in FIG. 11, the increase of an area due to the incorporation of the memory for a RAM test command inside the LSI, and a test of the memory itself for a RAM test command also become a problem. In the BIST circuit proposed in the patent document 2, although the increase of an area due to the addition of the memory for a RAM test command does not occur, the increase of an area due to signal lines or the like for drawing a program from the scan path register inside the LSI, which is used as the substitution for the memory for a RAM test command, and the deterioration of a wiring characteristic during layout become a problem. Also, since these test circuits generate a test pattern from a program, there is a defect that, in the RAM test control circuit and the test pattern generator, a circuit for conducting the decode of a program, the generation of a control signal of the RAM or the like is required, and a circuit size becomes larger.